Introducing Students to Open Hardware and RISC-V: My Remote Session at NSS College of Engineering

Earlier this month, I had the opportunity to conduct a remote RISC-V 101 session for students at NSS College of Engineering, my alma mater. Nearly 50 students joined live, asked enthusiastic questions, and stayed deeply engaged throughout the entire workshop.

This session was special for me because it brought together my ongoing work in RISC-V research and open hardware — and the place where my engineering journey began. I designed the talk as a beginner-friendly introduction to:

  • What open hardware means
  • Why Instruction Set Architectures matter
  • The origin and philosophy of RISC-V
  • The base RV ISA and its characteristics
  • Careers, mentorships, and opportunities in the open hardware ecosystem

The slides used in the session are from Insights on Open Hardware & RISC-V (PDF).

Setting the Stage: Why Open Hardware Matters

We began with an introduction to open hardware, a topic that many students had heard about but never fully explored. Using the definition from page 5 of my slides, we discussed how open hardware:

  • Makes designs publicly available
  • Encourages modification, distribution, and innovation
  • Mirrors the success of open-source software
  • Powers platforms like Arduino, Open Compute Project, and RISC-V

Students resonated strongly with the idea that open hardware removes barriers for experimentation — making it ideal for builders, researchers, and startups.

What is Open Hardware?

Understanding Computer Architecture From the Ground Up

Before diving into RISC-V, I wanted everyone to build intuition about how computers work.
Slides 7–12 walk through a conceptual buildup: how devices differ, what an ISA is, and why the boundary between hardware and software is so important.

On page 8 and 9, the slides show the ISA as the invisible “platform” where hardware supports software. This visual metaphor landed especially well — several students later messaged saying it finally “clicked” why ISAs matter.

We also discussed:

  • Why Intel cannot sell mobile chips
  • Why ARM does not dominate servers
  • Why ISA compatibility defines entire ecosystems
    (as explained clearly on Slide 10)

This is the perfect setup for explaining why an open ISA like RISC-V is revolutionary.

Why Instruction Set Matters

Introducing RISC-V: The Open Instruction Set

Around the midpoint of the session, we shifted into RISC-V fundamentals, beginning with the “What is RISC-V?” slides from pages 17–19.

We covered:

  • RISC-V started at UC Berkeley in 2010
  • It is fully open and available under a BSD license
  • It is modular with a small, elegant base ISA
  • It is designed for everything from microcontrollers to servers

I also showed historical slides where RISC-V is compared with earlier Berkeley RISC processors (page 19). Students were surprised to learn how deep the academic lineage is behind modern architectures.

We discussed global adoption (Slide 20), showing logos of companies from Google, Qualcomm, Intel, to ZTE. This helped students see that RISC-V is not a “future possibility” — it is already in shipping products.

RISC-V Base ISA and Extensions

The most technical part of the talk was a guided tour of the RV base ISA, starting with the diagram on Slide 24.
This slide shows:

  • The four base integer ISAs (RV32E, RV32I, RV64I, RV128I)
  • Only ~50 instructions needed for the base
  • Standard extensions: M, A, F, D, G, Q

This was the first exposure many students had to ISA modularity.

We discussed why the RISC-V base ISA remains stable (“frozen forever") — an important feature for ecosystem reliability.

RISC-V Base Plus Standard Extensions

A Peek Into Modern RISC-V Ecosystem

Slides 22, 25, 26, 27, and 28 show real world use cases across:

  • Storage devices
  • Edge computing
  • AI accelerators
  • Embedded controllers
  • High performance computing
  • Consumer devices

I emphasized how RISC-V is not just important for chip designers.
It opens opportunities in:

  • Compilers
  • Verification
  • Operating systems
  • Embedded development
  • ML accelerators
  • Hardware security

Several students said this changed their perception of hardware careers and made them consider RISC-V as a promising path.

Open Hardware Licensing

We also discussed licensing (Slide 29), where students learned about:

  • CERN OHL
  • TAPR OHL
  • BSD licensing in RISC-V
  • IP considerations for open hardware startups

This part sparked good discussion in the chat — many were curious about how companies use open ISA but protect their implementations. Slide 29 explained this clearly.

Showing the Path: Hands-on, Tools, and Opportunities

Toward the final part of the session, I introduced students to hands-on possibilities (Slide 30):

  • Using QEMU or Spike emulator
  • Building and running simple RISC-V programs
  • Toolchains like GCC and LLVM

I explained how anyone can get started with real RISC-V development today with zero hardware.

Slides 32 and 33 were especially meaningful because they connect RISC-V with my own journey.

Slide 33 lists how RISC-V mentorship opportunities changed my life:

  • LFX RISC-V mentorship
  • Travel fund to attend RISC-V Summit USA
  • My ongoing RISC-V research at UCSC

Students loved this part — many said they want to follow a similar path.

Participant Interaction and Live Q&A

Nearly 50 students attended, and the engagement was high throughout the session. Many questions centered around:

  • How to begin working in hardware without prior experience
  • How students can contribute to open source silicon projects
  • Whether RISC-V is a good career move (answer: absolutely yes)
  • The difference between RISC and CISC in real world applications
  • How to get involved in RISC-V Foundation activities

I also shared my website, GitHub, and personal contact details so anyone can reach out later — all of which are shown on Slide 36.

Personal Reflection

Giving this session felt both nostalgic and purposeful.

NSS College of Engineering is where my engineering journey truly started. Returning as a PhD student and RISC-V researcher to introduce juniors to open hardware felt like closing a loop.

The remote nature of the session worked surprisingly well — students interacted actively through voice and chat, shared reactions, and asked questions right until the end.

What made it even more fulfilling was realizing that many students had never seen a beginner friendly breakdown of hardware concepts, ISAs, and RISC-V significance before. The goal of the session was to ensure everyone left with:

  • A clear understanding of ISAs
  • Awareness of open hardware
  • Practical RISC-V knowledge
  • Motivation to explore the ecosystem

I believe we achieved that.

Conclusion

Open hardware represents the next wave of innovation.
And RISC-V — with its openness, flexibility, and growing global ecosystem — is at the heart of that future.

This session was a small step toward empowering students at NSSCE to explore hardware, build skills early, and become part of the global open silicon movement.

If you are a student reading this:
Start today. Experiment. Build. Join communities. Apply to mentorships.
Open hardware has space for everyone.

If you want the slides or want to host a RISC-V workshop at your institution, feel free to reach out anytime.