RISC-V Summit North America 2024: A PhD Student’s Deep Dive into the Open ISA Revolution

I was incredibly fortunate to attend the RISC-V Summit North America 2024 in Santa Clara, California, on a scholarship. As a PhD student actively working with RISC-V processors, the experience was truly immersive and fully packed with invaluable insights, connections, and hands-on learning. This year, attending as a researcher focused on processor design, the conference was the most enriching experience, offering a significant and targeted academic experience.

thanks to the media team for this wonderful picture

🗓️ Day 0: Members Day, Technical SIGs, and the Hackathon Challenge

My summit experience officially kicked off on Monday, October 21st, with Members Day. It was a day dedicated to in-depth technical discussions and collaborative working group meetings, setting a high-octane tone for the entire event.

Key Sessions & Technical Deep Dives

I focused on Member Day sessions highly relevant to my PhD research in hardware verification using advanced simulation and formal methods:

• Realizing RISC-V Certification, and What it Means for your Verification by Adnan Hamid (Breker) provided crucial context on industry expectations for core quality and the role of commercial-grade testing, directly impacting how we model and verify processors.
• Member Day Session: Verifying a CPU with Sail by Tim Hutt (Codasip) was a must-attend. Learning how companies like Codasip use the Sail open-source golden model for verification was an excellent deep dive into industry-standard simulation methods.
• Sailing Toward a Single Source of Truth by Paul Clarke (Ventana) and Derek Hower (Qualcomm) highlighted the importance of using formal ISA descriptions like Sail to generate verification artifacts, which is key to my research on robust processor models.
• RISC-V 101: This workshop demonstrated the foundational and growing educational efforts, emphasizing the community’s commitment to supporting newcomers and accelerating the adoption path.

The Hackathon Challenge: Hands-On Innovation

The definitive highlight of Day 0 was participating in the Hackathon. I teamed up with a group to tackle a problem posed by Codasip focused on optimizing certain workloads using RISC-V’s unique ability to utilize custom instructions. This was an intense but rewarding exercise, allowing me to apply my theoretical knowledge to a real-world, industry-relevant problem and collaborate with experienced engineers.

💡 Day 1: Keynotes, Industry Adoption, and Groundbreaking Research

Tuesday, October 22nd, exploded with a fantastic series of keynotes and breakout sessions that showcased the massive industry momentum behind RISC-V.

Main Stage: An Architecture Arrives

The morning keynotes were truly inspiring, emphasizing that RISC-V has well and truly “arrived” in high-performance computing and mobile.

• Keynote: RISC-V is Here! Innovation and Adoption Driving the Open Compute Future by Calista Redmond painted a clear picture of the open compute revolution and the incredible community growth (as noted by Anisha Sharma’s blog, the ecosystem is rapidly expanding toward 20 billion SoCs by 2031!).
• Keynote: Building Data Center Scale SoC’s using RISC-V at Meta by Prahlad Venkatapuram provided exciting insights into how major tech companies are leveraging RISC-V for cutting-edge, power-efficient, data center-scale hardware.
• Keynote: Unlocking Innovation with RISC-V and Qualcomm was a massive endorsement, highlighting the architecture’s push into the high-performance and mobile space, especially given the ratification of the RVA23 Profile requirements.

Technical Tracks: Verification and Design Tools

My focus on Day 1 was heavily geared toward the ISA and Design Tools track, where the discussion centered on verification best practices and performance modeling:

• Sail RISC-V: Status and Future Challenges detailed the latest updates and hurdles in maintaining the golden reference model, which is the cornerstone for all RISC-V verification efforts.
• RISC-V CPU Development Using Olympia Performance Model by Knute Lingaard (MIPS) provided a valuable overview of the Olympia Out-of-Order superscalar model. Understanding how this model is used for trade-off analysis before RTL design is vital for efficient design verification.
• Debug Signal Trace: HW Signal Capture in Post Silicon for Debug, Coverage and Performance Analysis from Sajosh Janarthanam (Tenstorrent) offered practical insights into debug methodologies that complement pre-silicon verification through simulation.

Poster Session & Networking Success

The afternoon Poster Sessions provided an excellent forum for focused discussion. I spent quality time engaging with cutting-edge research.

I was able to delve into the content of posters like “Instant RISC-V Migration of Golang Applications” and “CHERI-RISC-V from Academia to Industry”. More importantly, I had productive conversations about my PhD research with industry pioneers. It was here I had the pleasure of meeting David Patterson!. I made many new friends and built connections with renowned academics and leading industry professionals.

🤝 Day 2: Standards, Security, and The Future Ecosystem

The final day, Wednesday, October 23rd, reinforced the themes of robust standards, critical security, and the thriving software ecosystem.

Keynotes on Standards and Security

The final keynotes provided a clear view of the standards and industry outlook:

• Keynote: RISC-V ISA: State of the Union by Mark Himelstein offered a comprehensive overview of the numerous ratified and in-progress extensions, underscoring the rapid maturation of the ISA for new market segments.
• Keynote: Innovation Secured: A Paradigm Shift in the Processor Industry by Ron Black (Codasip) highlighted the critical importance of memory safety and security extensions, a theme echoed by the concurrent security tracks.

Technical Focus: Simulation, Security, and Debugging

The final day reinforced the critical role of robust verification and tooling, extending into the realms of security and high-performance computing:

• Software Simulation Is the Key to Success for Customized CPUs and Complex SoCs by Jon Taylor (Synopsys) was highly relevant, arguing that high-fidelity software models (virtual prototypes/ISS) enable faster architectural exploration and early software development—a core philosophy in simulation-based verification.
• Combined Dynamic and Formal Verification Approach to Processor Verification by Aimee Sutton (Synopsys) was a standout session, offering a practical strategy for achieving processor quality, which is paramount in verification engineering.
• RISC-V Control-Flow Integrity (CFI) and Hardening Linux and FreeBSD on RISC-V with CHERI were critical security talks demonstrating how advanced ISA extensions (like Zicfiss/Zicfilp and CHERI) are specified, which ultimately drives the complexity and focus of verification test benches.
• Ratified N-Trace Specifications - an Overview detailed the standardized debugging and tracing mechanisms that are essential for post-silicon validation, linking closely back to pre-silicon test planning.

Keynote Panel and Final Reflections

The final Keynote Panel: Chiplets in the RISC-V Ecosystem was a fantastic closing act.

The discussion emphasized a major trend in hardware design and how RISC-V’s open, modular ISA perfectly aligns with the future of heterogeneous compute and chiplet-based designs.

Attending the RISC-V Summit North America 2024 as a PhD student was truly an honor and a game-changer. The entire conference was a direct reflection of my research focus, feeling less like a general conference and more like a high-intensity professional development week. I leave the event with a stronger grasp of the RISC-V ecosystem, valuable new connections with both academicians and industry leaders, and a renewed drive to contribute to the open hardware revolution through my work on RISC-V processors. The scholarship truly enabled a fully packed and impactful experience!