LFX RISC-V Mentorship Experience: Building the Web Sliderules

During the Summer and Fall LFX cycle I had the incredible opportunity to work under Simone Shawn Cazzaniga in the LFX RISC-V Mentorship program. Our project was simple to describe but surprisingly deep once executed. The goal was to take Simone’s famous “Sliderules” RISC-V instruction sheets and turn them into a fully interactive web tool that can encode assembly into binary and decode binary into assembly. The final output became the RISC-V Web Sliderules, now live at:

https://sliderules.magiwanders.com

The mentorship was one of the most educational experiences of my RISC-V journey. It was both a deep dive into the ISA and an exercise in careful information design, accuracy, and correctness.

The poster was presented at RISC-V Summit 2023 China.

Introduction: What are the Sliderules

The original “Sliderules Cheatsheets” were created by Simone as a way to make the RISC-V ISA less intimidating. The official PDF is large and not very beginner friendly. Simone solved this by arranging instructions in a two dimensional layout so that students can “play assembler” and visually align opcodes, funct fields, and the immediate layouts. It became popular in universities and workshops because it makes bits tangible rather than abstract.

During the mentorship, our job was to go one level further. We needed to translate this static material into:

• a web friendly
• interactive
• instruction complete
• encoder and decoder

for RV32I, RV32M, RV32A, RV64, and the compressed ISA.

This meant handling more than eighty instructions, every bit field, every immediate shape, and every corner case in the spec.

Simone supervised and guided us throughout the entire process.

Working Under Simone: Learning the Real RISC-V Specification

Working with Simone was like having the RISC-V specification in human form. He has a unique ability to explain bit patterns, instruction formats, and field alignments in a way that actually makes them enjoyable. Every meeting involved understanding tiny details that I had never before appreciated, such as:

• Why some immediates are non contiguous
• How RISC-V packs bits to preserve alignment
• How signed immediates are read
• Why certain opcodes overlap
• How to detect ambiguous patterns
• How compressed instructions reuse register groups

The mentorship pushed me to read the official ISA documentation line by line. I can confidently say that this experience fundamentally improved my understanding of RISC-V beyond anything I had before. It made binary layouts feel natural rather than mysterious.

Porting the Cheatsheets to the Web

The project required translating the spreadsheet based cheatsheets into a functional encoder and decoder. This part was much harder than it sounds.

The spreadsheet contains:

• instruction row number
• mnemonic
• description
• type
• extension
• immediate shape
• which bits map to which field
• opcode
• funct3
• funct7
• funct2
• compressed quadrants
• pseudo-code

Our job was to convert this entire table into a machine readable format and then write logic that:

1. Converts assembly input into binary bits (encoder)
2. Takes a 32 bit binary pattern and identifies the correct instruction (decoder)
3. Displays the fields visually like real sliderules

The decoder especially required careful logic because multiple instructions can partially overlap. Correct matching requires:

• checking opcode
• checking funct3
• checking funct7
• checking fixed immediate field shapes
• checking register field positions
• checking the compressed instruction quadrant

This taught me a lot about how assemblers and disassemblers work under the hood.

Building the Bit Boxes UI

One of the most recognizable parts of the Web Sliderules is the row of thirty two visual squares for each bit. These can be:

• auto filled by the encoder
• user clickable for manual binary composition
• updated in real time while decoding

This visual layout mimics the physical sliderule idea. Simone insisted on this because it teaches the user to see how fields shift depending on instruction format.

For example, in an addi instruction, the immediate occupies bits 31 to 20, and rs1, funct3, rd, and opcode follow. But in a jal instruction, the immediate uses a scattered immediate format that students often struggle with.

Seeing the field boundaries move as the user selects bits makes the ISA much easier to memorize.

You can find the source code at: https://github.com/magiwanders/riscv_sliderules_cheatsheets

Example 1: Encoding jal x1, x2

Below is an example exactly like the one I tested on the live website:

Input:

jal x1, x2

Encoded output (Auto generated):

00000000000000000000000001101111

When this binary string is fed into the decoder, the tool breaks down:

• opcode
• immediate shape
• register fields
• format type
• pseudo-code

It correctly reconstructs the instruction.

(Your screenshot goes here.)

Example 2: Decoding 00000000100000010000000010010011

Another example tested on the site:

Binary input:

00000000100000010000000010010011

The web app decodes it as:

addi x1 x0

With the fields:

• ISA: RV
• Mnemonic: rd, rs1, imm
• Description: Add Immediate
• Architecture: 32 and 64
• Fields: opcode, funct3, rs1, rd

(Your screenshot goes here.)

This demonstrates that the decoder is fully ISA aware and can match the exact row from the original sliderules spreadsheet.

Supporting the Compressed ISA

One of the most challenging parts was adding support for the compressed ISA (RVC). Compressed instructions use sixteen bits instead of thirty two, and they reuse register encodings, immediate shapes, and opcodes in a very compact manner. The decoder needed:

• quadrant detection
• funct mapping for CI, CJ, CB, CA formats
• correct immediate expansion
• correct pseudo-op reconstruction

Simone guided me through every detail of the compressed ISA, including how to expand a sixteen bit instruction into its original form for easier display. Implementing support for RVC made the tool feel complete.

What I Learned from This Mentorship

This experience transformed how I understand instruction sets, bit encodings, and ISA design. Some of the most valuable lessons:

RISC-V is simple only on the surface

Once you dive into encoding, you realize how much design discipline goes into keeping the instruction set orthogonal and elegant.

Reading specifications is a skill

You do not just “read” the spec. You decode diagrams, split bitfields, understand pseudo-code, and map semantics to hardware.

Information design matters

Simone’s original sliderules proved that presenting information correctly can save countless hours for students.

Encoder and decoder logic follow a compiler mindset

This project helped me think like an assembler author, not just a hardware engineer.

Compressed instructions are underrated

Supporting RVC taught me how powerful compressed instructions are for reducing code size, yet they require careful binary layout handling.

Mentorship accelerates learning

Simone created a supportive environment where deep technical understanding felt natural rather than intimidating.

Looking Forward

The Web Sliderules currently support:

• RV32I
• RV32M
• RV32A
• RV64I
• Compressed RVC

The next steps are:

• supporting RV64GC fully
• adding real time program encoding
• integrating an educational mode
• exporting instruction sequences
• adding a visual pipeline of the immediate field
• connecting it with teaching tools at universities

I plan to continue contributing even after the LFX program because this tool genuinely helps beginners and even intermediate engineers.

Closing Thoughts

Participating in the LFX RISC-V Mentorship was one of the most formative experiences of my academic and engineering life. Working with Simone enhanced my understanding of the ISA, improved my ability to read dense technical documents, and taught me how to turn static educational material into a living, interactive tool.

The Web Sliderules now serve as a resource for anyone learning RISC-V. I am proud of the work we accomplished and grateful for the mentorship, guidance, and encouragement that made it possible.