Chip Productivity using LLMs
My current focus of work is leveraging LLMs for chip producitivty, which I’ll be working during my docotoral research at MASC Group (Micro Architecture at Santa Cruz), lead by Professor Jose Renau. Stay tuned to my blogs for getting updates about what I’m doing.
RISC-V Web Sliderules
I contributed to the “Sliderule” Encoder and Decoder Cheat Sheets project, which condenses RISC-V specification details into a visual, easy-to-understand format for educational use. My contribution includes extending the content to cover the RV64GC architecture and creating an interactive web interface that allows users to explore subsets of information and generate PDFs. The goal of this project is to provide a user-friendly tool for learning the RISC-V instruction set.
- Key Contributions:
- Expanded the content to RV64GC architecture.
- Developed an interactive web interface for exploring and generating PDFs.
- Aimed at simplifying learning and reference for the RISC-V instruction set.
Source code: Not public yet (as of 07/23), will be released soon.
RiVulet - RISC-V Disassembler based on Sliderules
I am currently developing RiVulet, an RV64GC-compatible disassembler. This project builds upon the data structure developed during the RISC-V Web Sliderules project. The disassembler can also be used as an API, and I’m actively working on making it compatible with RV32|64I instruction sets.
- Key Features:
- RV64GC-compatible disassembler.
- Can function as an API.
- Actively under development with current work focused on RV32|64I.
Source code: gitlab.com/jyrj/RiVulet
CalibrateSDR
This project was part of my work for AerospaceResearch.net, supported by the Google Summer of Code 2021. I worked on signal standards such as NWS, 3G, and 4G, focusing on calibration using the sync pulses embedded within these signals. Additionally, I ported the tool to Python for signal processing tasks.
- Key Contributions:
- Worked on calibration using sync pulses in signals like NWS, 3G, and 4G.
- Ported the tool to Python for enhanced signal processing.
Source code: github.com/aerospaceresearch/CalibrateSDR
Verification using LLM (Under Development)
I am currently developing a verification tool that uses Large Language Models (LLMs) to generate test cases during the post-silicon validation stage. This tool is specifically targeted for use with the RV[32|64]G instruction sets. The project is still in its early development stage, and the source code will be released after the first alpha version is ready.
- Key Features:
- Leverages LLMs for test case generation.
- Targeted for post-silicon validation of RV[32|64]G architectures.
Source code: github.com/jyrj/VerifAIyer (private, will be released)